Digital phase-locked loop

ABSTRACT

Disclosed is a digital phase-locked-loop including: a time-to-digital converter (TDC) configured to output a digital bit based on an input clock and a reference clock, in which the TDC includes: a first arbiter group configured to compensate for a phase difference between the input clock and the reference clock with a first average offset and output a first logic value; a second arbiter group configured to compensate for a phase difference between the input clock and the reference clock with a second average offset and output a second logic value; and a signal processor configured to output the digital bit based on the first and second logic values.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application claims priority to and the benefit of Korean PatentApplication No. 10-2013-0026891 filed in the Korean IntellectualProperty Office on Mar. 13, 2013, the entire contents of which areincorporated herein by reference.

TECHNICAL FIELD

The present invention relates to a digital phase-locked loop, and moreparticularly, to a digital phase-locked loop including a time-to-digitalconverter (TDC) of which an operation range is expanded by using atleast two flip-flops or latches having different offsets.

BACKGROUND ART

According to the recent development of technology, a digitalphase-locked loop (ADPLL) has been widely used instead of a charge-pumpphase-locked loop (CPPLL) having a problem of an analog circuit.

A time-to-digital converter is a significant configuration in thedigital phase-locked loop performing the same function as that of aphase-frequency detector (PFD) in the charge-pump phase-locked loop inthe related art.

However, the time-to-digital converter, for example, a delay-line basedTDC, a stochastic TDC, a time-amplifying TDC, and a ring-oscillatorbased TDC, of the related art is operated only as a phase-detector (PD)in terms of a narrow operation range.

The phase-detector (PD) may be operated only when a difference betweentwo frequencies is very small, and in a case where a loop band range isdecreased in order to decrease jitter, there is a problem in that anoperation range of the phase-detector is also decreased.

Recently, researches for expanding an operation range of thetime-to-digital converter have currently been conducted.

SUMMARY OF THE INVENTION

The present invention has been made in an effort to provide a digitalphase-locked loop including a time-to-digital converter (TDC) of whichan operation range is expanded by using at least two flip-flops orlatches having different offsets.

An exemplary embodiment of the present invention provides a digitalphase-locked-loop including: a time-to-digital converter (TDC)configured to output a digital bit based on an input clock and areference clock, in which the TDC includes: a first arbiter groupconfigured to compensate for a phase difference between the input clockand the reference clock with a first average offset and output a firstlogic value; a second arbiter group configured to compensate for a phasedifference between the input clock and the reference clock with a secondaverage offset and output a second logic value; and a signal processorconfigured to output the digital bit based on the first and second logicvalues.

The digital phase-locked loop according to the exemplary embodiment ofthe present invention includes a plurality of arbiter groups havingdifferent average offsets, so that it is possible to form atime-to-digital converter having an operation range expanded to theoffset standard deviation by adjusting the average offset.

The digital phase-locked loop according to the exemplary embodiment ofthe present invention includes the time-to-digital converter of which anoperation range is expanded, so that it is possible to improveresolution by adjusting a specification of the time-to-digitalconverter.

The foregoing summary is illustrative only and is not intended to be inany way limiting. In addition to the illustrative aspects, embodiments,and features described above, further aspects, embodiments, and featureswill become apparent by reference to the drawings and the followingdetailed description.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a control block diagram illustrating a control configurationof a digital phase-locked loop according to an exemplary embodiment ofthe present invention.

FIG. 2 is a control block diagram illustrating a first exemplaryembodiment of the control configuration of a time-to-digital converter(TDC) illustrated in FIG. 1.

FIG. 3 is a circuit diagram schematically illustrating thetime-to-digital converter illustrated in FIG. 2.

FIG. 4 is an offset distribution diagram formed of first and secondarbiter groups illustrated in FIG. 2.

FIG. 5 is a control block diagram according to a second exemplaryembodiment of the control configuration of the time-to-digital converter(TDC) illustrated in FIG. 1.

FIG. 6 is a circuit diagram schematically illustrating thetime-to-digital converter illustrated in FIG. 5.

It should be understood that the appended drawings are not necessarilyto scale, presenting a somewhat simplified representation of variousfeatures illustrative of the basic principles of the invention. Thespecific design features of the present invention as disclosed herein,including, for example, specific dimensions, orientations, locations,and shapes will be determined in part by the particular intendedapplication and use environment.

In the figures, reference numerals refer to the same or equivalent partsof the present invention throughout the several figures of the drawing.

DETAILED DESCRIPTION

Contents below are simple examples of a principle of the invention.Accordingly, a person skilled in the art may implement the principle ofthe invention and invent various apparatuses included in a concept and ascope of the invention although it is not clearly described orillustrated in the present specification. All conditional terms andexemplary embodiments enumerated in the present specification areclearly intended only for the purpose of understanding the concept ofthe invention in principle, and shall not be understood that theconditional terms and exemplary embodiments are limited to the speciallyenumerated exemplary embodiments and states.

It shall be understood that all detailed descriptions enumerating aspecific exemplary embodiment, as well as the principle, the aspect, andthe exemplary embodiments of the present invention are intended toinclude a structural and functional equivalent thereof. It shall beunderstood that the equivalents include an equivalent to be developed inthe future, that is, every element invented so as to perform the samefunction regardless of a structure, as well as a currentlypublicly-known equivalent.

Accordingly, for example, a block diagram in the present specificationshould be understood to indicate an exemplary conceptual point of viewfor embodying a principle of the present invention. Similarly, all ofthe flowcharts, state conversion diagrams, and pseudo codes, should beunderstood to be substantially expressed in computer-readable media andto express a variety of processes performed by a computer or aprocessor, regardless of whether the computer or the processor isclearly illustrated.

Functions of various devices illustrated in the drawings includingfunctional blocks that are expressed as a processor or a concept similarthereto may be provided for use of dedicated hardware and use ofhardware having capability to execute software in association withappropriate software. When the functions are provided by a processor,the functions may be provided by a single dedicated processor, a singleshared processor, or a plurality of individual processors, and a partthereof may be shared.

Clear use of the processor, control, or terminology proposed as asimilar concept thereto should not be interpreted by exclusively citinghardware having the capability to execute software, and should beunderstood to allusively include digital signal processor (DSP)hardware, and ROM, RAM, and a non-volatile memory for storing softwarewithout restriction. Publicly known and commonly used other hardware maybe included.

In the claims of the present specification, constituent elementsexpressed as means for performing functions described in the detaileddescription are intended to include, for example, all methods performinga function including a combination of circuit elements performing thefunction or all types of software including a firmware/microcode, andare combined with a circuit appropriate for executing the software so asto perform the function. Since the invention defined in the claims iscombined with functions provided by various numerated means and combinedwith a scheme demanded by the claim, any means capable of providing thefunction should be understood to be an equivalent to that recognizedfrom the present specification.

The aforementioned objects, characteristics, and advantages will be moreapparent through the detailed description below related to theaccompanying drawings, and thus those skilled in the art to which thepresent invention pertains will easily implement the technical spirit ofthe present invention. In the following description, a detailedexplanation of known related functions and constitutions may be omittedso as to avoid unnecessarily obscuring the subject matter of the presentinvention.

Hereinafter, an exemplary embodiment according to the present inventionwill be described in detail with reference to the accompanying drawings.

FIG. 1 is a control block diagram illustrating a control configurationof a digital phase-locked loop according to an exemplary embodiment ofthe present invention.

Referring to FIG. 1, the digital phase-locked-loop includes atime-to-digital converter (hereinafter, referred to as a “TDC”) 110, adigital loop filter (hereinafter, referred to as a “DLF”) 120, a digitalcontrolled oscillator (hereinafter, referred to as a “DCO”) 130, and adivider 140.

The TDC 110 outputs a digital bit (not illustrated) based on a referenceclock Fdiv output from the divider 140 and an input input clock Fref.

The digital bit of the TDC 110 corresponds to a phase difference and afrequency difference between the reference clock Fdiv and the inputclock Fref, and the TDC 110 performs the same function as that of aphase-detector on the phase-locked loop by an analog scheme.

The DLF 120 outputs a frequency control word (FCW) in which the digitalbit output from the TDC 110 is filtered.

That is, in the DLF 120, an input and an output are all digital signals,and a low band pass filter function, such as a loop filter of an analogphase-locked loop, may be implemented by using a digital logic, but theDLF 120 is not limited thereto.

Here, the FCW is a control signal for decreasing a phase differencebetween the reference clock Fdiv and the input clock Fref, but is notlimited thereto.

The DCO 130 outputs an output clock Fdco, of which an output frequencyis changed with the FCW output from the DLF 120, to the divider 140.

The divider 140 feeds back the reference clock Fdiv, which is obtainedby dividing the output clock Fdco output from the DCO 130 by apredetermined dividing value N, to the TDC 110.

FIG. 2 is a control block diagram illustrating a first exemplaryembodiment of the control configuration of a time-to-digital converter(TDC) illustrated in FIG. 1, FIG. 3 is a circuit diagram schematicallyillustrating the time-to-digital converter illustrated in FIG. 2, andFIG. 4 is an offset distribution diagram formed of first and secondarbiter groups illustrated in FIG. 2.

Referring to FIGS. 2 to 4, the TDC 110 includes first and second arbitergroups 122 and 124, and a signal processor 126.

Here, each of the first and second arbiter groups 122 and 124 mayinclude at least one of at least two flip-flops and latches, but is notlimited thereto.

In the exemplary embodiment, it is described that each of the first andsecond arbiter groups 122 and 124 includes the plurality of flip-flops,but the present invention is not limited thereto.

It is described that the plurality of flip-flops 122_1 to 122_N, and124_1 to 124_N are D flip-flops, and the reference clock Fdiv and theinput clock Fref are input to each of the plurality of flip-flops 122_1to 122_N, and 124_1 to 124_N, and each of the plurality of flip-flops122_1 to 122_N, and 124_1 to 124_N outputs a logic value for the phasedifference between the reference clock Fdiv and the input clock Fref.

First, at least one of the plurality of flip-flops 122_1 to 122_Nincluded in the first arbiter group 122 may have an offset differentfrom that of another flip-flop, but is not limited thereto.

Accordingly, the plurality of flip-flops 122_1 to 122_N included in thefirst arbiter group 122 may have a first average offset, and transmits afirst logic value including a logic value output from each of theplurality of flip-flops 122_1 to 122_N to the signal processor 126.

The first logic values may be probability values for the logic valuesoutput from the plurality of respective flip-flops 122_1 to 122_N, andthe probability values may be distributed based on the first averageoffset.

At least one of the plurality of flip-flops 124_1 to 124_N included inthe second arbiter group 124 may have an offset different from anotherflip-flop, and is not limited thereto.

Accordingly, the plurality of flip-flops 124_1 to 124_N included in thesecond arbiter group 124 may have a second average offset, and transmitsa second logic value including a logic value output from each of theplurality of flip-flops 124_1 to 124_N to the signal processor 126.

The second logic values may be probability values for the logic valuesoutput from the plurality of respective flip-flops 124_1 to 124_N, andthe probability values may be distributed based on the second averageoffset.

Here, the signal processor 126 may accurately determine a timedifference compensating for the offset based on the logic values outputfrom the plurality of respective flip-flops 122_1 to 122_N, and 124_1 to124_N included in the first and second arbiter groups 122 and 124, thatis, information on a time difference at rising edges between thereference clock Fdiv and the input clock Fref.

That is, the signal processor 126 may include an adder 126_1 for addingthe first and second logic values, and an inverse function signalprocessor 126_2 for processing inverse function signals for the firstand second logic values added in the adder 126_1, and outputting thequantized and delayed digital bit.

Here, the offset distribution diagram illustrated in FIG. 4 may have theGaussian distribution in which a general arbiter group has astatistically ideal offset, and an offset average value (μ=0), and hasan average value ((μ=td) of any one of the first and second arbitergroups 122 and 124, and may have an average value (μ=−td) of the otherone thereof.

In this case, the first and second arbiter groups 122 and 124 may havethe first and second offset average values (μ=td and μ=−td), which areformed wider than the offset average value (μ=0), so that the operationrange of the TDC 110 may be increased.

In the exemplary embodiment, it is described that the TDC 110 includesthe two first and second arbiter groups 122 and 124, but the TDC 110 mayinclude three arbiter groups as illustrated in FIG. 4, and the offsetaverage values of the three arbiter groups may be combined to have μ=0,μ=td, and μ=−td, respectively. Accordingly, as a distribution of thecombined offset average values is wide, the operation range of the TDC110 may be increased.

As described above, when the operation range of the TDC 110 isincreased, resolution may be decreased, and the resolution and theoperation range may be adjusted.

FIG. 5 is a control block diagram illustrating a second exemplaryembodiment of the control configuration of a time-to-digital converter(TDC) illustrated in FIG. 1, and FIG. 6 is a circuit diagramschematically illustrating the time-to-digital converter illustrated inFIG. 5.

Referring to FIGS. 5 to 6, the TDC 110 includes the first and secondarbiter groups 122 and 124, and the signal processor 126, and a delayelement unit 128.

Here, each of the first and second arbiter groups 122 and 124 mayinclude at least one of at least two flip-flops and latches, but is notlimited thereto.

In the exemplary embodiment, it is described that each of the first andsecond arbiter groups 122 and 124 includes the plurality of flip-flops,but the present invention is not limited thereto.

It is described that the plurality of flip-flops 122_1 to 122_N, and124_1 to 124_N are D flip-flops, and the reference clock Fdiv and theinput clock Fref are input to each of the plurality of flip-flops 122_1to 122_N, and 124_1 to 124_N, and each of the plurality of flip-flops122_1 to 122_N, and 124_1 to 124_N outputs the logic value for the phasedifference between the reference clock Fdiv and the input clock Fref.

First, at least one of the plurality of flip-flops 122_1 to 122_Nincluded in the first arbiter group 122 may have an offset differentfrom that of another flip-flop, but is not limited thereto.

Accordingly, the plurality of flip-flops 122_1 to 122_N included in thefirst arbiter group 122 may have a first average offset, and transmits afirst logic value including a logic value output from each of theplurality of flip-flops 122_1 to 122_N to the signal processor 126.

At least one of a plurality of flip-flops 124_1 to 124_N included in thesecond arbiter group 124 may have an offset different from anotherflip-flop, and is not limited thereto.

Accordingly, the delay element unit 128 is disposed at a front end ofthe TDC 110 so that the plurality of flip-flops 124_1 to 124_N includedin the second arbiter group 124 may have a second average offset, and asa result, the plurality of flip-flops 124_1 to 124_N transmit secondlogic values including the logic values output from the plurality ofrespective flip-flops 124_1 to 124_N to the signal processor 126.

Here, the logic value output from each of the plurality of flip-flops122_1 to 122_N, and 124_1 to 124_N included in the first and secondarbiter groups 122 and 124 may be varied according to a time differencecompensating for an offset according to a time difference at risingedges between the reference clock Fdiv and the input clock Fref.

The delay element unit 128 phase-delays the reference clock Fdiv totransmit the phase-delayed reference clock Fdiv to the second arbitergroup 124.

That is, the reference clock Fdiv transmitted to the second arbitergroup 124 has a difference from the reference clock Fdiv transmitted tothe first arbiter group 122 by a phase delay time set in the delayelement unit 128.

The signal processor 126 may include the adder 126_1 for adding thefirst and second logic values, and the inverse function signal processor126_2 for processing inverse function signals for the first and secondlogic values added in the adder 126_1, and outputting a quantized anddelayed digital bit.

In the exemplary embodiment, it is described that the TDC 110 includesthe two first and second arbiter groups 122 and 124, but the TDC 110 isnot limited thereto.

That is, in a case where the TDC 110 includes three arbiter groups, theoffset distribution diagram illustrated in FIG. 4 may have the Gaussiandistribution in which a general arbiter group has a statistically idealoffset, and an offset average value (μ=0), and has an average value(μ=td) of any one of the first and second arbiter groups 122 and 124,and may have an average value ((μ=−td) of the other one thereof.

In this case, the first and second arbiter groups 122 and 124 have thefirst and second offset average values (μ=td and μ=−td), which areformed wider than the offset average value (μ=0), so that the operationrange of the TDC 110 may be increased.

As described above, when the operation range of the TDC 110 isincreased, resolution may be decreased, and the resolution and theoperation range may be adjusted.

As described above, the exemplary embodiments have been described andillustrated in the drawings and the specification. The exemplaryembodiments were chosen and described in order to explain certainprinciples of the invention and their practical application, to therebyenable others skilled in the art to make and utilize various exemplaryembodiments of the present invention, as well as various alternativesand modifications thereof. As is evident from the foregoing description,certain aspects of the present invention are not limited by theparticular details of the examples illustrated herein, and it istherefore contemplated that other modifications and applications, orequivalents thereof, will occur to those skilled in the art. Manychanges, modifications, variations and other uses and applications ofthe present construction will, however, become apparent to those skilledin the art after considering the specification and the accompanyingdrawings. All such changes, modifications, variations and other uses andapplications which do not depart from the spirit and scope of theinvention are deemed to be covered by the invention which is limitedonly by the claims which follow.

What is claimed is:
 1. A digital phase-locked-loop, comprising: atime-to-digital converter (TDC) configured to output a digital bit basedon an input clock and a reference clock, wherein the TDC comprises: afirst arbiter group configured to compensate for a phase differencebetween the input clock and the reference clock with a first averageoffset and output a first logic value; a second arbiter group configuredto compensate for a phase difference between the input clock and thereference clock with a second average offset and output a second logicvalue; and a signal processor configured to output the digital bit basedon the first and second logic values.
 2. The digital phase-locked loopof claim 1, wherein each of the first and second arbiter groups includesat least two flip-flops or latches.
 3. The digital phase-locked loop ofclaim 1, wherein each of the first and second arbiter groups includes atleast two flip-flops or latches, and at least one of the at least twoflip-flops or latches has an offset different from that of anotherflip-flop or latch.
 4. The digital phase-locked loop of claim 1, whereinthe first average offset is different from the second average offset. 5.The digital phase-locked loop of claim 1, wherein the first arbitergroup includes a plurality of flip-flops, and each of the plurality offlip-flops compensates for a phase difference between the input clockand the reference clock with a predetermined offset, and transmits thefirst logic value to the signal processor.
 6. The digital phase-lockedloop of claim 1, wherein the second arbiter group includes a pluralityof flip-flops, and each of the plurality of flip-flops compensates for aphase difference between the input clock and the reference clock with apredetermined offset, and transmits the second logic value to the signalprocessor.
 7. The digital phase-locked loop of claim 1, furthercomprising: a phase delay unit configured to phase delay the input clockinput in the second arbiter group.
 8. The digital phase-locked loop ofclaim 1, wherein the signal processor comprises: an adder configured toadding the first and second logic values; and an inverse function signalprocessor configured to process inverse function signals for the firstand second logic values added in the adder and output the quantized anddelayed digital bit.